When the system logic circuit is tested incorporated into the semiconductor integrated circuit by a scan design formed from a scan chain, a bypass logic circuit is additionally provided around RAM incorporated in the semiconductor integrated circuit. During the test of the system logic circuit, a signal is arranged so as to bypass the RAM. Thereby, an improvement in the fault coverage in the system logic circuit and a decrease in the number of test patterns can be realized. In general, RAM is additionally provided with a custom-designed built-in self-test (hereinafter, referred to as “BIST”) circuit having built-in memory, and is tested independently of the system logic circuit. However, in an at-speed test for testing AC failures, a test configuration, which causes a signal to bypass RAM during the test of the system logic circuit, poses a problem.
An AC scan test; e.g., a transition test or a path test, is used for the at-speed test of the system logic circuit. Further, an at-speed memory BIST test performed by a memory BIST circuit is applied to the at-speed test of RAM. However, the at-speed test of a memory peripheral logic circuit cannot be conducted by the AC scan test or the at-speed memory BIST test. It is originally hard for the bypass logic circuit, which has been additionally provided for testing the system logic circuit, to perform at-speed operation. The bypass logic circuit is handled as a timing false path. Since the timing false Path is excluded from an object of test during generation of a AC scan test pattern. Hence, the at-speed test of a peripheral logic section of RAM cannot be performed.
A method for conducting the at-speed test of the peripheral logic section of RAM is to use an original path, which accesses RAM without passing through the bypass logic circuit, is used at the time of generation of a test pattern for an AC scan test in the system logic circuit (see, e.g., JP-A-2004-334933). At this time, an automatic test pattern generation (ATPG: Automatic Test Pattern Generation) tool, which generates a test pattern in a system logic circuit, must be able to generate a test pattern by comprehending operation of RAM. However, an ATPG tool using a memory operation model is different from a combinational ATPG tool for use with a simple combinational logic circuit, and must use a sequential algorithm which enables handling of a sequential circuit. An ATPG tool having a sequential algorithm using a memory operation model is longer in execution time than the combinational ATPG tool. The number of generated test patterns becomes very long. The reason for this is that logic, which is a combination of memory peripheral logic and a memory operation model, becomes very complicated.